This application is based upon and claims the benefit of Japanese Patent Applications No. 2000-79344 filed on Mar. 16, 2000, and No. 2000-79346 filed on Mar. 16, 2000, the contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor device including a power MOSFET and peripheral devices, and a method for manufacturing the same.
2. Description of Related Art
The Applicant proposes, in Japanese Patent non-published application No. 2000-10350, a semiconductor device (MOSFET) capable of reducing an ON resistance by setting a channel width parallel to a substrate depth direction. The MOSFET adopts an n+ type substrate that functions as a drain region. Meanwhile, it is required to form peripheral devices such as a CMOS for monitoring a temperature, a diode, and a MOSFET for controlling the power MOSFET on one chip together with the power MOSFET described above. That is, these peripheral devices and the power MOSFET are required to be formed on an identical substrate.
Therefore, when the n+ type substrate is used for the power MOSFET, the peripheral devices must be formed in the n+ type substrate other than the region where the power MOSFET is formed. However, this makes it difficult to control concentrations of diffusion layers for the peripheral devices. Further, the peripheral devices must be isolated from the drain region (the n+ type substrate 1) of the power MOSFET.
The present invention has been made in view of the above problems. An object of the present invention is to make it easier to control a concentration of a diffusion layer for a peripheral device that is formed together with a power MOSFET in an identical substrate. Another object of the present invention is to provide a semiconductor device including a power MOSFET and a peripheral device, which can be formed in an identical substrate by a simplified manufacturing method.
According to a first of the invention, a first conductivity type high-concentration semiconductor substrate has a first trench at a power MOSFET formation region for forming a power MOSFET, and a second trench at a peripheral device formation region for forming a peripheral device. A second conductivity type well layer is disposed in the second trench.
According to a second aspect of the invention, a first conductivity type high-concentration semiconductor substrate has a second conductivity type semiconductor layer thereon. A peripheral device is formed in the semiconductor layer except a region where a power MOSFET is formed. In these semiconductor devices, a concentration of a diffusion resistance of the peripheral device can be controlled easily despite the high-concentration substrate including the power MOSFET and the peripheral device together.
According to a third aspect of the invention, a peripheral device has a similar structure as that of a power MOSFET. Specifically, the peripheral device is a first conductivity type channel MOSFET composed of a well layer of a first conductivity type extending in a semiconductor substrate, a base region of a second conductivity type extending in the well layer, a semiconductor region of the first conductivity type extending in the base region, a trench dividing the semiconductor region into a source region and a drain region, a gate insulating film provided on an inner wall of the trench, and a gate electrode provided on a surface of the gate insulating film and filling the trench.
In this case, the peripheral device can be manufactured at the same manufacturing steps as those for the power MOSFET simultaneously, resulting in a simplified manufacturing method. The peripheral device is not limited to the first conductivity type channel MOSFET as mentioned above, but may be a second conductivity type channel MOSFET. Otherwise, the peripheral device can include both the first conductivity type channel MOSFET and the second conductivity type channel MOSFET, i.e., n-channel MOSFET (nMOS) and p-channel MOSFET (pMOS).